Magnetic random access memory (MRAM) that incorporates a magnetic tunnel junction (MTJ) as a memory storage device is a strong candidate to provide a high density, fast (1-30 ns read/write speed), low power, and non-volatile solution for future memory applications. The architecture for MRAM devices is composed of an array of memory cells generally arranged in rows and columns. Each memory cell is comprised of a memory element (MTJ) that is in electrical communication with a transistor through an interconnect stack. The memory elements are programmed by a magnetic field created from pulse current carrying conductors such as copper lines. Typically, two arrays of current carrying conductors that may be called “word lines” and “bit lines” are arranged in a cross point matrix. Normally, the word lines are formed under the MTJs and are isolated from the memory elements by one or more layers such as an etch stop layer and an interdielectric (ILD) layer. The bit lines contact the top portion of the MTJs and are electrically connected to a conductive cap layer. Additionally, there is a bottom electrode (BE) that contacts the bottom of each MTJ and electrically connects the MTJ with an underlying transistor.
The MTJ consists of a stack of layers with a configuration in which two ferromagnetic layers are separated by a thin insulating layer such as AlOX that is called a tunnel barrier layer. One of the ferromagnetic layers is a pinned layer in which the magnetization (magnetic moment) direction is more or less uniform along a preset direction and is fixed by exchange coupling with an adjacent anti-ferromagnetic (AFM) pinning layer. The second ferromagnetic layer is a free layer in which the magnetization direction can be changed by external magnetic fields. The magnetization direction of the free layer may change in response to external magnetic fields which can be generated by passing currents through a bit line and word line in a write operation. When the magnetization direction of the free layer is parallel to that of the pinned layer, there is a lower resistance for tunneling current across the insulating layer (tunnel barrier) than when the magnetization directions of the free and pinned layers are anti-parallel. The MTJ stores digital information (“0” and “1”) as a result of having one of two different magnetic states.
In a read operation, the information is read by sensing the magnetic state (resistance level) of the MTJ through a sensing current flowing through the MTJ, typically in a current perpendicular to plane (CPP) configuration. During a write operation, the information is written to the MTJ by changing the magnetic state to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents. Cells which are selectively written to are subject to magnetic fields from both a bit line and word line while adjacent cells (half-selected cells) are only exposed to a bit line or a word line field.
As the MTJ size from a top-down view shrinks relative to the easy axis and hard axis directions (x,y plane), and from a cross-sectional perspective is reduced in thickness (perpendicular to the x,y plane) in order to satisfy higher performance MRAM requirements, the interconnects within the MRAM structure also decrease in size to conform to electrical requirements and space restrictions for high density designs. There is also a greater demand on reliability of the MRAM device since reduced MTJ sizes usually lead to a greater chance of device failure at contact points between adjacent metal layers and tend to cause delamination of the one or more interlevel dielectric (ILD) layers that separate the bit line and word line during CMP processing. In particular, the ILD layer above the word line and below the MTJ tends to delaminate during CMP processes to planarize the MTJ and bit line (BIT).
In order to maximize word line and bit line writing efficiency in an MRAM device, one needs to minimize both the distance from the bit line (BIT) to the MTJ free layer and the distance from the word line (WL) to the MTJ free layer. In related patent application Ser. No. 11/724,435, a MTJ mask layout was described that enables a reduction in the BIT-MTJ distance. In state of the art MRAM designs, there are only BE and ILD layers separating the WL and MTJ. The BE thickness is normally thin so the best approach to minimize the WL-MTJ distance is to reduce the ILD thickness. However, there are some major obstacles in this approach. First, there is a lack of high etch selectivity between BE films and ILD films. Secondly, an over-etch non-uniformity across a substrate due to etch tool hardware limitations and an etch micro-loading effect between dense and isolated features prevents a smooth and thin ILD layer. Moreover, as an ILD layer becomes thinner, it is more susceptible to delamination during chemical mechanical polish (CMP) processes. In addition, as an ILD layer becomes thinner, the risk of etch chemical leakage through pinholes and attacking the WL increases. Therefore, an improved BE mask layout is required to enable thinner ILD layers without suffering from the aforementioned drawbacks.
A routine search of the prior art revealed the following reference. In U.S. Pat. No. 6,358,755, a dummy bottom electrode may be formed in addition to a bottom electrode in a memory cell where a metal plug and bottom electrode form an electrical connection between a ferroelectric capacitor and an integrated circuit transistor. However, the circuit does not include a MTJ as required for a MRAM device fabrication.